PDN Design Reference Card
Power Delivery Network · High-Speed PCBs
© Fresu Electronics · All rights reserved · Do not reproduce
Core Formulas
Max frequency of power bus
fmax = 0.5 / tr
tr in ns · result in GHz
0.5 ns → 1 GHz
250 ps → 2 GHz
50 ps → 10 GHz
0.5 ns → 1 GHz
250 ps → 2 GHz
50 ps → 10 GHz
Target PDN impedance
Zt = Vnoise / Iinst
Vnoise = max tolerable noise (V)
Iinst = outputs × mA per output
50 out × 40 mA = 2 A
100 mV / 2 A = 50 mΩ
Iinst = outputs × mA per output
50 out × 40 mA = 2 A
100 mV / 2 A = 50 mΩ
Energy circle radius
r = tr × 6 in/ns
Place caps within this radius
250 ps → 0.75 in reach
500 ps → 1.50 in reach
250 ps → 0.75 in reach
500 ps → 1.50 in reach
Dario Fresu
Principal EMC Architect
IPC CID · Former ETH Zurich
4,000+ engineers trained
4,000+ engineers trained
Via Inductance Rules
Key principle
Inductance belongs to the pair, not a single via. Spacing dominates — not diameter, not length.
↓ 60% reduction · no size change · spacing only
Capacitor Package Inductance
| Package | Typical L | Note |
|---|---|---|
| 1206 (end via) | ~1250 pH | Avoid for HF |
| 0805 (end via) | ~1050 pH | — |
| 0603 (end via) | ~900 pH | — |
| 0402 | ~560 pH | — |
| 0201 | ~450 pH | — |
| 1206 side via | ~450 pH | = 0201 if correct |
| 0603 side 2× vias | ~250 pH | Best for size |
Frequency → Delivery Tool
< 1 MHz
VRM / bulk capacitors
1–100 MHz
Mid-value ceramics (10–100 µF)
100–400 MHz
0.1 µF / 0.01 µF ceramics
> 400 MHz
Low inductance only — planes + via pairs
Capacitor Mounting Rules
✓ Do
Side-mount vias · opposite polarity adjacent · same side as IC · within energy circle
✗ Don't
End-mount on high-speed · same polarity adjacent · opposite board side · crowd under BGA
Plane Spacing Impact
| Plane separation | Classification | PDN use |
|---|---|---|
| > 11 mil (0.28 mm) | Wide | DC only — caps do all HF work |
| 6–11 mil | Medium | Some HF benefit |
| < 6 mil | Close | Dominates HF delivery |
| 2–4 mil (HDI) | Optimal | Planes beat caps above 400 MHz |
Inductance is a per-square measurement — depends on separation, not area. A 1-inch square and 10-inch square at equal spacing have equal inductance.
IC Placement vs Inductance
✓
Board center — full circular energy field, minimum inductance
△
Board edge — semicircle, moderate inductance increase
✗
Board corner — quarter circle, significant inductance increase · avoid for high-current ICs
Stackup Design Guide
4-LAYER STANDARD — AVOID
L1Signalmicrostrip
L2Power~1 mm gap ↓
L3Ground~1 mm gap ↑
L4Signalmicrostrip
Plane cap ≈ useless · 1 cap beats both planes
── improved approach ──
6-LAYER + COPPER POURS — RECOMMENDED
L1Signal + GND pour↑ field boundary
L2Power pourthin dielectric
L3Signal + Pwr pour
L4Signal + Pwr pour
L5Ground pourthin dielectric
L6Signal + GND pour↓ field boundary
10× lower inductance vs standard 6-layer
8 Rules · Apply Before Layout
01Calculate Ztarget before placing any component
02Always pair power + ground vias — minimize spacing
03Side-mount vias on decoupling caps · opposite polarity adjacent
04Caps same side as the IC — always, no exceptions
05High-current ICs at board center
06Close-coupled planes (<6 mil) beat caps above 400 MHz
07Copper pours + stitch every λ/10 · min 2 vias per island
08Below 400 MHz: add capacitance · Above: reduce inductance