A practical engineering guide to PDN design: target impedance, via inductance, capacitor mounting strategy, and board stackup configuration — from low-speed microcontrollers to multi-gigabit systems.
Most engineers are taught that voltage and current are where the energy is. It's a reasonable starting point — but it's incomplete. Energy in a circuit lives in the electric and magnetic fields, not in the conductors that carry current.
When a signal trace runs above a reference plane, energy doesn't travel through the copper. It travels through the dielectric space between them — the PCB substrate material. The copper generates electron movement, but the energy itself propagates through the insulating space.
Power delivery works the same way. If your power plane is on layer 2 and your ground plane is on layer 5, power is being delivered from the dielectric space between them — not from the copper layers themselves.
The goal of power distribution design is to maintain low bus impedance across a defined frequency band — from the clock frequency up to a maximum defined by signal rise time.
Target impedance is derived from your noise budget. Divide the maximum acceptable noise voltage on the supply rail by the maximum instantaneous current draw.
All high-frequency instantaneous current is drawn during the rise time of output signals — the brief window when a logical zero transitions to a logical one. This is when every milliohm of PDN impedance matters.
Inductance cannot be calculated for a single isolated via. Inductance is a property of a pair — specifically, the loop formed by a power via and its return (ground) via. The spacing between them dominates the result, not their diameter.
Why? Because energy lives in the magnetic field between the two vias. The larger the separation, the larger the magnetic field volume — and inductance scales with field volume. Bring the vias together and the field condenses into a smaller, tighter space. Inductance falls sharply.
Always pair power and ground vias as closely as the design allows. The partial inductance of a single via is meaningless — what matters is the loop inductance of the power-ground pair.
The package size of a decoupling capacitor matters far less than how it's attached to the board. Via placement and polarity arrangement determine the effective inductance — and the difference between a well-mounted and poorly-mounted cap can be a factor of 4x in inductance.
Opposite polarity vias must be adjacent. When two vias of the same polarity sit next to each other, their magnetic fields repel. When a positive and negative via are adjacent, their fields attract and partially cancel — this is what lowers inductance. Never place same-polarity vias side by side on a high-frequency decoupling capacitor.
Always mount decoupling capacitors on the same side of the board as the IC they serve. Routing to the opposite side dramatically increases the inductance of the delivery path. With microcontrollers, this single rule often matters more than capacitor value.
The correct decoupling strategy depends entirely on signal rise time. Low-speed and high-speed boards have opposite requirements in some key areas — applying the wrong approach to the wrong board creates problems rather than solving them.
Max frequency: 125–250 MHz. Capacitors alone handle this — no power plane needed. Mount caps near IC pins on same board side. Vias at outer edges of capacitor intentionally increase inductance to decouple the IC from the power rail (the origin of the term "decoupling capacitor").
Closely-spaced planes dominate because their inductance is lower than the capacitor attachment inductance. Capacitors dump energy into the planes; planes deliver to the IC. Capacitor location within an energy circle matters more than proximity to the IC.
Energy in FR4 travels at roughly half the speed of light — approximately 6 inches per nanosecond. The energy circle radius is: rise time (ns) × 6 inches/ns. A 500 ps rise time means a 1.5-inch energy circle.
Plane inductance is a per-square measurement — it depends on the separation between power and ground planes, not on the physical area of the board. A 1-inch square of planes separated by 4 mil has the same inductance as a 10-inch square at the same separation.
This has important implications for IC placement. An IC at the center of the board has full circular energy fields — lowest inductance. An IC placed at an edge loses part of its circle. An IC in a corner loses two sides of its energy field — dramatically increasing inductance.
High-current, high-speed ICs belong in the center of the board. Not at corners, not at edges.
With power and ground planes separated by ~1 mm (typical 4-layer board), the plane capacitance is almost negligible. A single 0.1 µF ceramic capacitor delivers more usable energy than those planes across virtually the entire frequency range. This is why capacitors are essential even when planes are present.
Board stackup is one of the highest-leverage decisions in PDN design. Two boards with identical components and routing can have 10× different PDN inductance based solely on stackup choices.
Copper pours must be properly stitched. Any isolated copper island with fewer than two vias connecting it to a reference should be removed. Pour ground on top and bottom signal layers, connect overlapping pours with vias every 1/10th wavelength of the highest frequency in the design.
For high-layer-count boards (>8 layers) operating at multi-gigabit speeds, the optimal configuration places power-ground plane pairs near the surface — adjacent to the BGA. When planes are close to the surface, mounting decoupling capacitors on the top of the board (rather than under the BGA) reduces the via loop area and delivers measurably lower impedance.
Calculate Z target before layout. Maximum noise voltage ÷ peak instantaneous current = your impedance budget. Design the PDN to stay below this value across the full frequency band.
Spacing dominates via inductance. Move power-ground via pairs as close together as your design rules allow. A 60% inductance reduction is achievable without changing via size.
Side-mount decoupling vias. Place vias at the sides of capacitors, not the ends. Opposite polarity must be adjacent. Each additional via pair halves the inductance.
Same side as the IC — always. Place decoupling capacitors on the same PCB side as the IC they serve. Routing to the other side of the board dramatically increases attachment inductance.
High-speed ICs at board center. Edge and corner placement cuts the energy field circle, increases per-square inductance, and reduces effective decoupling bandwidth.
Pair planes — and put them close. Widely-spaced power and ground planes (>11 mil apart) offer minimal decoupling benefit. Close-coupled planes (<6 mil) can outperform dozens of capacitors.
Use copper pours, stitch them properly. Ground pours on signal layers reduce PDN inductance by up to 10× on constrained layer-count boards. No isolated pour should exist without at least two stitching vias.
Low frequency = capacitance. High frequency = inductance. At MHz frequencies, add more capacitance. Above ~400 MHz, low inductance is the only lever that works — capacitance cannot help.
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