Signal Integrity Reference Card
High-Speed PCB Design · Field-Centric Approach
© Fresu Electronics · All rights reserved · Do not reproduce
Core Formulas
Signal bandwidth from rise time
BW = 0.35 / tr
tr in ns → BW in GHz
1 ns → 350 MHz
500 ps → 700 MHz
100 ps → 3.5 GHz
1 ns → 350 MHz
500 ps → 700 MHz
100 ps → 3.5 GHz
Critical length — terminate if longer
lc = (tr/6) × vp
vp ≈ 6 in/ns in FR4
1 ns → 1.0 in
500 ps → 0.5 in
250 ps → 0.25 in
1 ns → 1.0 in
500 ps → 0.5 in
250 ps → 0.25 in
Reflection coefficient
Γ = (ZL−Z₀)/(ZL+Z₀)
Γ=0 → perfect match (no reflection)
Γ=+1 → open circuit
Γ=−1 → short circuit
Γ=+1 → open circuit
Γ=−1 → short circuit
Ground bounce voltage
ΔV = Lpkg × di/dt
Lpkg = package inductance
5 nH × 1 A/ns → 5 V spike
5 nH × 1 A/ns → 5 V spike
3W crosstalk rule
s ≥ 3 × w
s = edge-to-edge spacing
w = trace width
Reduces lateral field coupling ~70%
w = trace width
Reduces lateral field coupling ~70%
Dario Fresu
Principal EMC Architect
IPC CID · Former ETH Zurich
4,000+ engineers trained
4,000+ engineers trained
Signal Propagation
Core principle
A signal is an EM field in the dielectric between conductors — not electrons in copper. Both the signal trace and return reference plane are equally required to contain and guide it.
| Parameter | Governs |
|---|---|
| Rise time (tr) | Bandwidth, critical length, termination need |
| Clock frequency | Repetition rate only — not the SI parameter |
| Dielectric εᵣ | Propagation speed: vp = c/√εᵣ |
| Propagation speed | ≈ 6 in/ns (FR4) · ≈ 8 in/ns (Rogers) |
Return Path Rules
✓ Do
Solid reference plane beneath every signal layer. Return via at every layer transition. Zone-based partitioning for analogue/digital.
✗ Avoid
Routing over gaps or slots. Split planes to "isolate" circuits. Layer transitions without return via. Isolated copper islands.
Return Current by Frequency
| Frequency | Dominant impedance | Return path |
|---|---|---|
| < 1 kHz | Resistance | Spreads across full plane area |
| 1 kHz – 1 MHz | Mixed | Partially beneath trace |
| > 1 MHz | Inductance | Directly beneath signal trace |
Impedance Control
| Variable | Increase | Effect on Z₀ |
|---|---|---|
| Trace width (w) | ↑ | Z₀ ↓ |
| Dielectric height (h) | ↑ | Z₀ ↑ |
| Dielectric constant (εᵣ) | ↑ | Z₀ ↓ |
Standard targets: 50 Ω single-ended · 100 Ω differential (loosely coupled) · 90 Ω differential (USB)
Termination Strategy
| Type | Placement | Best for | Trade-off |
|---|---|---|---|
| Series (Rs) | At source | Point-to-point | No DC draw. Half-amp at load. |
| Parallel (Rp) | At load | Clean waveform needed | Continuous DC current |
| AC / Thevenin | At load | CMOS, no DC allowed | Adds capacitance |
| None | — | Electrically short lines | Only valid below lc |
Myth buster
Adding termination to short traces wastes power and slows edges. Calculate l_crit first — if the trace is shorter, do not terminate.
Crosstalk (NEXT / FEXT)
Mechanism
Capacitive + inductive coupling from aggressor to victim. NEXT at near end. FEXT at far end. Grows with parallel coupling length and falls with spacing.
✓3W rule: edge-to-edge ≥ 3× trace width
✓Route adjacent layers orthogonally — eliminates layer-to-layer coupling
✓Stripline > microstrip for sensitive signals (two planes contain field)
✗Long parallel runs even at 3W accumulate crosstalk — keep parallel length short
Differential Pairs
| Parameter | Requirement |
|---|---|
| Length matching | Within 10% of UI, or per spec |
| Intra-pair spacing | Tight coupling — maintain throughout route |
| Diff. impedance | 100 Ω (LVDS, PCIe) · 90 Ω (USB) |
| Serpentine spacing | ≥ 3× trace width in meanders |
| Reference plane | Continuous under full pair length |
Stackup Reference
AVOID — No adjacent reference planes
L1Signaluncontained fields
L2Power~1mm gap ↓
L3Ground~1mm gap ↑
L4Signaluncontained fields
── better approach ──
GOOD — Signal adjacent to reference
L1Signal + GND pourfield boundary
L2Ground plane2–4 mil ↕
L3Signal (stripline)
L4Signal (stripline)
L5Power plane
L6Signal + GND pourfield boundary
8 Rules — Apply Before Layout
01Think in fields. SI is a field containment problem.
02Rise time governs. Calculate BW=0.35/tr before routing.
03Solid reference plane. No gaps under high-speed signals.
04Return via at every layer transition. No exceptions.
05Control impedance end-to-end. Every via and connector counts.
06Terminate only electrically long lines. l > l_crit.
073W rule + orthogonal layer routing. Eliminate crosstalk.
08Strong PDN = SI prerequisite. Ground bounce corrupts signals.